Enhanced direct digitizing array arrangement

ABSTRACT

The invention comprises an array of ADCs, associated either with spatially separated signal input devices such as for example antennae, or with a single signal input device and a plurality of filters having a variable phase delay, which provide a digital output which is processed to remove spurious signals introduced by the ADCs thereby providing a linearised output. An array of N antennae with respective band pass filters and ADCs ( 10 ) feeds received signals into a frequency channelisation device ( 12 ) which divides each of the N input streams into M lower bandwidth streams for distribution. In a first path, an FFT ( 14 ) is used to detect signal of interest, to determine where intermodulation products arm likely to exist and to provide course data for the spatial processing used in the signal separation sub-systems. The second path ( 16 ) includes the detection and separation of co-channels signals. Signal classification techniques are then used to identify spurious sir, which are then removed.

This invention relates to that of an array of ADCs, separated eitherspatially or with filters having a variable phase delay, which is such aconfiguration, can provide a higher dynamic range Analogue to Digitalconversion than was previously achievable, one application of which is adirect digitising array for radio frequency receivers.

BACKGROUND

Analogue to Digital Converters (ADCs), have been found wanting in the RFarea where they are used to convert analogue narrow band IF in areceiver to the digital domain so that demodulation can be performed inways that can not be achieved using traditional analogue equivalents.

The following description uses the RF area as a good example of anapplication of the beneficial application of ADCs but it will beapparent to those skilled in the art that the real advance disclosedherein is the novel approach of using an ADC array and the provision ofa method to nullify the effects of the inherent non-linearity of ADCs.

Analogue RF front ends for receivers are still preferably used todaysince:

-   -   1. the dynamic range of wide band digitising systems are seen as        inferior to that obtained from analogue filters, and    -   2. the signal processing needed for wide-bandwidth processing is        deemed to be both beyond the capacity of affordable DSP engines        and unnecessary for an individual receiver which normally        attempts to tune only one signal at any instant in time.

During the recent past, these beliefs have become less true, but thehighest performing receivers are still undoubtedy analoguesuperheterodynes that subsequently use digital demodulation techniques(i.e. an analogue front-end with the more flexible digital backend).

Since most users look at the performance of individual receivers, theconventional wisdom is that direct digitising receivers are inferior.

However, a receiver site that shares multiple antennae amongst multiplereceivers can make the direct digitizing approach competitive with andpotentially exceed conventional analogue systems.

In a large analogue receiver system, there are a number of antennaeshared by a number of users. This results in a need to split theincoming RF energy from all the antennae so that any one operator canreceive a desired frequency using one or more beams pointing in roughlythe right direction. However, every time the received signal is splitthere is a loss in fidelity (i.e. the Signal to Noise Ratio (SNR) gets alittle worse). Further, when independent signals are combined to givedirectional beams, the finite accuracy of the combiners (typically 2degrees at 0.1 dB) means that the beams are not precise. Moreover, thisapproach requires a dedicated receiver for every user, thus users mustaccept the “best available” beam even if it's not exactly appropriate atthe time and even if an unwanted signal (interference) is also on thatchannel at that time.

Despite these compromises, analogue techniques work. It is howeverunlikely that any major advance in performance using these techniques isachievable as this technology is well developed.

In the analogue domain, the overall system performance is limited by theperformance of the RF front end. However, it is proposed that the use ofa suitable analogue to digital architecture can create a digital domainin which appropriate use of signal processing techniques can compensatefor many of the imperfections of the conversion process in the front-endthus overall enhancing the system performance.

A single ADC handling two large in-band signals F1 and F2 will, due tonon-linearity in the ADC, particularly in the Sample and Hold, producespurious harmonics and intermodulation products in the output spectrumat F1+F2, 2F1−F2 etc. Thus any small signal on those particularfrequencies would be difficult if not impossible to detect or copy,where copy is used to mean reception and demodulation of the transmittedsignal without error. Where these harmonics and intermodulation productslie above the Nyquist frequency, they will appear as aliased in-bandcomponents with the output of the ADCs. Thus, the largestintermodulation products are considered to limit the useful dynamicrange of an ADC.

In an example, a more realistic situation in the H.F. band would be 50large signals each being 3 kHz wide. This would generate about 2000 inband 2^(nd) order, 5000 in band 3^(rd) order intermodulation terms.Making some reasonable assumptions of the degree of overlap from theintermodulation products and also realising that the 2^(nd) orderproducts are 6 kHz wide, 3^(rd) order 9 kHz etc., the total bandwidthcorrupted by spurious signals occupies about 25 MHZ of the nominal 30MHz bandwidth for H.F. Thus, the intermodulation performance determinesthe performance of a single channel-digitising receiver.

However, if an array of these ADCs were connected to a spatiallydispersed antenna array, their largest intermodulation products nolonger constitute a performance limit. We can assume that the same twolarge signals we will still experience the same spurious frequenciesfrom each ADC, but each would have their own apparent angle of arrival.Hence, the Signals Of Interest (SOI) from other directions can still bereadily separated using conventional co-channel separation techniques,even if the SOIs are much smaller than the interfering spurious signal.

Using the above approach, it is possible to accept the limited spuriousfree dynamic range (SFDR) of individual ADC channels induced by ADCnon-linearities, but provide a higher system SFDR by using advancedsignal processing techniques to remove the spurious signals and so allowsmall signals which are below the noise floor of individual ADCs to bereceived for analysis and copy. This approach effectively ‘linearises’the non-linear ADCs.

Thus the use of an array of ADCs separated either spatially or withfilters having a variable phase delay can provide a higher dynamic rangeAnalogue to Digital conversion than previously achievable therebyoffering an alternative arrangement for the use of ADCs than waspreviously available and also allows for the use of lesser quality ADCsin an arrangement that provides equal or better performance than asingle ADC of higher quality.

BRIEF DESCRIPTION OF THE INVENTION

In its broadest aspect, the invention comprises an array of ADCs,associated either with spatially separated signal input devices such asantennae, or with filters having a variable phase delay, which providesa digital output which is processed to remove spurious signalsintroduced by said ADCs thereby providing a linearised output.

In a further aspect of the invention, an analogue to digital converter(ADC) apparatus for converting one or more analogue signals arriving ata plurality of spatially separated receiver elements comprising: arespective plurality of ADCs receiving from said receiver elements, aversion of said one or more analogue signals and converting saidanalogue signals into digital representations of said analogue signalsplus spurious components created by said ADCs; a processing means toidentify in said digital representations the spurious components byanalysis of the phase relationships of the spectral components of saidone or more analogue signals and spurious components according to thespatial relationships between each receiver element and said analoguesignals and spurious components; and a filter means to remove saidspurious components from said digital representations of said one ormore analogue signals.

In a further aspect of the invention the processing means furthercomprises statistical analysis and separation of independent signalcomponents, and a means to classify signals into spurious components andnon-spurious signals.

In a further broad aspect of the invention, an analogue to digitalconversion (ADC) apparatus for converting one or more analogue signalsarriving at a receiver element comprising: a plurality of ADCs providedrespectively with a variable phase delayed version of said one or moreanalogue signals and converting said analogue signals into digitalrepresentations of said analogue signals plus spurious componentscreated by said ADCs; a processing means to identify in said digitalrepresentations the spurious components by analysis of the phaserelationships of the spectral components of said one or more analoguesignals and spurious components according to said phase delays; and afilter means to remove said spurious components from said digitalrepresentations of said one or more analogue signals.

A yet further aspect of the invention is a method for removing spuriouscomponents from a digital representation of one or more analogue signalsgenerated by a non-linear analogue to digital conversion processcomprising the steps of:

-   -   a) receiving at a plurality of spatially separated receiver        elements said one or more analogue signals;    -   b) receiving at a respective plurality of analogue to digital        converters variable phase delayed versions of said analogue        signals for converting said analogue signals into digital        representations of said signals plus spurious components created        by said ADCs;    -   c) processing said digital representations to identify said        spurious components by analysis of the phase relationships of        the spectral components of said one or more analogue signals and        spurious components according the spatial relationships between        each receiver element and said signals and said spurious        components; and    -   d) filtering to remove said spurious components from said        digital representation of said one or more analogue signals.

A yet further aspect of the invention is a method for removing spuriouscomponents from a digital representation of one or more analogue signalsgenerated by a non-linear analogue to digital conversion processcomprising the steps of:

-   -   a) receiving at a receiver element said one or more analogue        signals;    -   b) receiving at a respective one of said plurality of analogue        to digital converters (ADC) a variable phased delayed version of        said analogue signals and converting said analogue signals into        digital representations of said signals plus spurious components        created by said ADCs;    -   c) processing said digital representations to identify said        spurious components by analysis of the phase relationships of        the spectral components of said one or more analogue signals and        spurious components according the respective phase delays; and    -   d) filter ing to remove said spurious components from said        digital representation of said one or more analogue signals.

Specific embodiments of the invention will now be described in somefurther detail with reference to and as illustrated in the accompanyingfigures. These embodiments are illustrative, and not meant to berestrictive of the scope of the invention. Suggestions and descriptionsof other embodiments may be included but they may not be illustrated inthe accompanying figures or alternatively features of the invention maybe shown in the figures but not described in the specification.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a functional architecture of an embodiment of an RFreceiving system;

FIG. 2 depicts a functional block diagram of an embodiment of theinvention in the RF field using multiple receiving elements;

FIG. 3 depicts a functional block diagram of an embodiment of theinvention in the RF field using multiple receiving elements withchannelising and synthesis;

FIG. 4 depicts a functional block diagram of an embodiment of theinvention in the RF field using a single receiving element;

FIG. 5 depicts a functional block diagram of an embodiment of theinvention in the RF field using a single receiving element withchannelising and synthesis; and

FIG. 6 depicts a phase-frequency relationship between the real andimaginary intermodulation products the imaginary of which are generatedby non-linearity in the A-D conversion process.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

It will be appreciated by those skilled in the art, that ADCs are usedextensively in the electronics field to translate analogue signals intodigital representations of those analogue signals. Such analogue signalsare obtained from many different types of sensors some examplesincluding strain gauges, voltage/current measuring devices, temperaturemeasurement devices, etc. Therefore, it will be apparent to those samepersons skilled in the art, that the concepts of this invention willprovide an improvement in the translation of analogue signals into thedigital domain where ever ADCs are used.

A specific embodiment of the invention comprises an array of antennae,each with its own wide band receiver or ADC, refer FIGS. 2 and 3. FIG. 3differs from FIG. 2 in that FIG. 3 includes channelisation and synthesisfunctional blocks that assist in paralleling the computation of theprocessing task. One form of channelisation is the division intoindependent frequency bands. Examples of the implementation ofchannelising in the frequency domain are the use of poly-phase filtertechniques or Fast Fourier transform techniques. Channelising in otherdomains (e.g. code or spatial) are also possible.

A further embodiment of the invention comprises the use of a singleantenna that provides variable phase delayed versions of the analoguesignals it receives into multiple ADCs, refer FIGS. 4 and 5. FIG. 5differs from FIG. 4 in that FIG. 5 includes channelisation and synthesisfunctional blocks that assist in paralleling the computation of theprocessing task as discussed above. Clearly, the single antennaembodiment is akin to the use of a single receiver element such as astrain gauge or other type of sensor when the invention is applied in anon-RF-based example.

In the FIGS. 2-5 the symbols Σ[a_(i1)]+Σ[s_(j1)] represent the summationof the quantised analogue signals and the quantised spurious signals.While the same symbols without [ . . . ] brackets represent unquantisedsignals.

Beneficially, the ADC elements need not be of particularly high quality(low linearity, etc.) since it is possible having taken this approach,to adequately filter out unwanted frequencies even those generated bythe non-linearity of the ADCs. Once the received analogue frequenciesare digitised, the following functionality can be achieved by digitalsignal processing. Receiver architectures of this type have a number ofimportant potentially advantageous features.

-   1. The splitting of digital data for distribution to multiple users    is lossless—there is no degradation over a single user-   2. Optimum beam formation: each user can optimise the RF spatial    pattern they use to maximise the SNR/Signal to Interference/or    ameliorate fading etc-   3. The system will be easier to upgrade, and with computer power    always increasing there is a growth path.-   4. It is possible to carry out automatic multi-dimensional    searching, allowing some signals to be detected even if there is a    large interfering signal or intermodulation product on the same    frequency (i.e. search in Frequency/Elevation/Azimuth)-   5. It should be cheaper to maintain, run and add additional users    etc-   6. It should be more general purpose than a conventional system    (i.e. the same hardware should be able to cope with conventional,    TDMA and CDMA signals by reprogramming and should not need unique    hardware for each)-   7. It will allow different algorithms to be implemented, as they    become available or are needed. As an example, altering the antenna    pattern to track a signal using information from the demodulators is    achievable using software alone.

A number of possible architectures for an RF receiver can be considered,most of them based on:

-   -   1. Multiple Wide band ADCs (say 32 ADCs each operating at 80        MHz)    -   2. Reducing each to narrower bandwidth channels (say 8 channels        each of 5 MHz bandwidth/10 MHZ sampling rate) in order to        provide more suitable data rate for subsequent processing units.    -   3. A multi-channel FFT engine in order to detect new signals in        Frazel (Frequency—Azimuth and Elevation) space.    -   4. For each radio operator there is an effective multi-channel        digital receiver bank to provide an optimised version of the SOI        (Signal Of Interest) by converting it to baseband,    -   4.1 Removing in-band spurious signals, separating signals of        interest from interference and remaining spurious signals which        in the technique by which the ADCs are linearised; and    -   4.2 Ameliorating fading effects due to multi-path propagation        etc.

A functional architecture of an embodiment of an RF receiving system isdepicted in FIG. 1. An array of N antennae with respective band passfilters and ADCs (10) feeds received signals and added spurious signalsinto a frequency channelisation device (12) which divides each of the Ninput streams into M (M may be 1 or more) predetermined bandwidthstreams for distribution. The choice of particular bandwidth streamswill depend on the information content of the analogue signal beingreceived or expected to be received at the antennae.

In a first path, an FFT (14) is used to detect signals of interest, todetermine where intermodulation products are likely to exist and toprovide coarse data for the spatial processing used in the signalseparation sub-systems. An alternative RP receiver architecture todetect signals of interest could occur as part of the signal separationprocess.

The second path (16) includes the detection of co-channels signals usingalgorithms such as Eigenvalue Decomposition. If these co-channel signalsare spatially distinct they are separated using spatial processingalgorithms such as, MUSIC and generalized side lobe cancellation and ifthey are spatially indistinct they are separated by Higher OrderStatistical (HOS) processing algorithms such as Joint ApproximateDiagonalization of Eigen-matrices (JADE). Signal classificationtechniques are then used to identify spurious signals, which are thenremoved. These processes linearise the output of the ADCs.

The final stage in the process is the demodulation and decoding (18) ofthe signals of interest.

Controlling the total system will be a control and recording system(20), that is typically accessed by a pool of users (22) each of whomare interested in a particular SOI at any one time.

Clearly, the invention is adapted to the RF receiver arrangement, butits primary architecture is evident in the array of ADCs, separatedeither spatially or with filters having a variable phase delay which insuch a configuration can provide a higher dynamic range Analogue toDigital conversion than previously achievable.

In this embodiment, assume the receiver front end has N (32) Analogue toDigital Converters each operating at 80 MHz. In other applicationsvariable and non-uniform sampling may be more appropriate and will givegreater bandwidth for the same input and output conditions and allowsspurious signals to be more readily identified and thus allows forgreater rejection of those signals. In order to provide the bestlinearity from each channel it is possible for a non-linear correctionsystem to be used on each channel that is similar to those based on workby Tsimbinos and Lever in the IEEE International Conference onAcoustics, Speech and Signal Processing, April 1994. As an example, toapply non-linear correction to a 20 MHz ADC requires 10 Gigaops ofprocessing, so that the total processing for 32 channels at about 80 MHzis about 32×40 Gigaops=1.2 Teraops.

The data distribution system in which the input data is split intonarrow bandwidth streams based on the frequency bandwidth of interestoccurs in the frequency channelisation device (12). This is not strictlya desirable attribute, but the input data stream is 32 channels×80MHz×16 bits=40 Gbits/second because it is beyond the capacity of currentdata buses. However if the raw input were divided into 8 data streams(by frequency) and a switching network provided to allow any subsequentprocessing to select which ever data stream it required they would eachonly require about 4 Gbits/second of bandwidth which should beavailable. In order to divide each of the 32 input streams into 8 therewill need to be a filtering process that may be implemented as a seriesof 7 half band filters each of which would need to be at least a 20 tapfilter. Thus the total processing in this data split, ignoring dataseparation and switching, is approximately 32 channels×80 MHz×7filters×40 operations=716 Gflops. A further way to channelize is tosub-sample all the individual ADC rates or reduce their sampling rates.Provided that the total sample rate exceeds Nyquist, it is possible touse the spatial information to unambiguously identify and separate allthe signals. In the spatial example it is a preferred embodiment thatthe separation would be done by Ricatti number theory.

At this point there are two separate paths, the first being the signaldetection path (used to detect signals of interest, to determine whereintermodulation products are likely to exist and to provide coarse datafor the spatial processing used in the signal separation sub-systems).In that case, 32 channels of 10 MHz data will undergo a Fourier analysisand then subsequent processing to look for signals of interest. For theH.F. band a 100 Hz resolution is needed, and as such 100 FFTs per secondeach of length 128K would be needed. A 128K FFT involves about 8.7million floating operations, and as such this stage will require 32channels×100 FFTs/second×8.7 million operations=28 Gflops. However,following the Fourier transforms there is a second level of processingto combine the 32 channels spatially and to look for new signals. Thisleads to a processing demand similar to that of the FFT, and as such, itwould be reasonable to allocate approximately 60 Gflops to thissub-system.

As depicted in FIG. 1 there is a signal separation and detection path,and there will need to be a separate system for each user. In the caseof a preferable H.F. communications installation there are likely to beabout 20 operator positions. For the first co-channel separation processeach of the 32 channels is first reduced to a 10 KHz bandwidth usingdigital filtering techniques. A preferred example is a Digital DownConverter (DDC) and a dual rate filter. Typically the first filter willbe a fast, but short FIR (say of the order 10 at the 10 MHz datarate—say about a 20 Mflops processing power requirement). Afterdecimation (to, say a 1 MHz rate) there is a second longer filter (atthe 1 MHz rate of order 100—say about a 20 Mflops processing powerrequirement) followed by decimation to the final 10 kHz bandwidth. Thusthe ‘narrow band receivers’ have a total processing load of about 32channels×20 Mflops=640 Mflops.

Following this there is a processing stage to provide the spatialprocessing, and possibly the HOS to identify and remove interference andintermodulation products. Different algorithms have very differentprocessing loads, but the main factor is the number of antennas used,since this determines the number of in-band signals that can beseparated. If there were 32 elements one could theoretically separate 31signals, though in practice 20 would be more reasonable. One of thesimpler algorithms requires about 4.Q² operations per data point where Qis the number of channels used. A 10 kHz data rate would need a 40Mflops processor. Many other algorithms such as Joint ApproximateDiagonalization of Eigen-matrices (JADE) require several orders ofmagnitude higher processing throughput but this provides a realisticminimum processing load for the system.

The final stage in the process is the demodulation and decoding of thesignal of interest, but given that this occurs with a single 10 kHz datastream it is likely to be less than 5 Mflops and as such can beneglected in this calculation.

Total Processing

It is now possible to see that the total processing requirement fordigital receiving station with 32 antennas and 20 users is likely to be

-   -   Front End 1200 Gflops    -   Separation 680 Gflops    -   Signal Search/Detection 60 Gflops    -   Co-Channel 20 channels @ 40 Mflops 1 Gflops        Thus, the total processing need is likely to exceed 2 Tera-flops

These figures are based on an indicative architecture and other variantswould increase the processing load considerably due to the needs ofother signal types. For example many systems used in the UHF bandrequire the co-channel algorithms to operate over a signal bandwidth upto 3 MHz wide rather than the 3 kHz assumed here, which could addanother 1000 Gigaflops to the co-channel separation processing load.

There are also good reasons to allow the demodulation/decoding algorithmoutputs for a Signal of Interest to control the co-channel separation,or for higher order filters to be used in the initial separationsub-system, all of which could have profound ramifications on the actualprocessing load required.

In the embodiment disclosed herein, it is possible to use commercialADCs preferably those with the best linearity. It is useful however todiscuss current ADC performance and appreciate that ADCs with lesserlinearity are also capable of being used as the subsequent digitalprocessing can compensate for the results of their non-linearity.

ADC performance has been improving at a rate of about 1.5 bits every 6-8years, and there became available an ADC with 14 bit linearity at 100Msamples/second on the market in the year 2000. This is not, by itselfadequate for a single channel H.F. receiver but it does offer alinearity of about 80 dB in the normal two-tone tests in which dynamicrange is governed by the SFDR.

There is also research into optical ADCs which may result in animprovement in performance (e.g. greater than 100 dB SFDR with greaterthan 100 MHz bandwidth), and further research into non-linearcompensation techniques will improve the linearity of existing ADCs.Furthermore, there are programs to improve the dynamic range of ADCs.

The concepts disclosed herein would benefit from any improvement inperformance but they are not predicated on it.

In a normal RF environment, there are a large number of ‘big’ signals.For the purposes of estimation, it is assumed that there are between 10and 50 such signals. In this case the largest signals in band are not ashigh as are used in testing the “two-tone dynamic range” and in manycases this means that a higher performance is possible, possibly closerto 90 dB SFDR

Spatial Spread of Intermodulation Products

A significant factor when considering the use of ADCs is that there willbe spurious signals generated by them, commonly referred to as “birdies”especially from the larger received signals. However, the inventors haverealized that this is not necessarily a disadvantage. Since thesebirdies have an apparent spatial origin, known co-channel techniques canbe used to remove them in a similar way to other signals of interest.

One simple way in which this can be described is to say that, if anarray is used rather than just a single receiver, the signals, noise andintermodulation products can be located in Frequency, Azimuth andElevation (Frazel) space. It is known that any two signals in this spacecan be separated if they are located in different Frazel bins. Forexample if we have only one ADC we might have 10,000 frequency channelsand if there were 5,000 birdies then half of the possible channels arefilled. However, if we use an array of antennae, we would still have thesame 10,000 frequency channels, but we also have 100 elevation anglesand 300 azimuth bins. Tis means that the 5,000 birdies lie in300,000,000 bins. If we assume a uniform distribution of signals, theprobability that an SOI is co-located with a birdie is now only 1 in60,000 which is no longer a problem.

Although this specification describes the benefits of the spatialseparation of receivers, it should be noted that an array of ADCsseparated by filters with a phase delay that varies with frequency couldperform the same operation on single channel data. This is a consequenceof the fact that most intermodulation products would have differentphase relationships to real signals and this can be used to discriminateagainst them. Thus, this method can offer a generic approach toimproving the performance of ADCs.

Co-channel separation algorithms are known in the art. The most commontechniques are known for their ability to separate signals and can befound in texts such at Tsui, James Bao-yen, “Digital MicrowaveReceivers”, 1989 Artec House, Inc.

Ghost Intermodulation Products

Other processing steps can improve the performance of the digitalapproach.

Since most of the intermodulation products do not come from physicallyrealizable directions (i.e. are ghosts) they can be filtered out. Asimple crossed array can remove about 75% of these products and a 3Darray which is not practical for H.F., but is realizable at higherfrequencies, can remove about 87% of the intermodulation products.

The mechanism behind this reduction can be explained by considering auniform linear array in which 50% of the intermodulation products can beremoved.

If there are a number of large signals that can create intermodulationproducts each of the large signals S_(i) arrives from some specific Lineof Bearing (LOB)_(i) and is at some specific wavelength λ_(i), and ifthe antenna array has an element spacing of D equal to a half wavelengthspacing at the highest frequency of interest, then the actual signalshave a phase difference from one element to another ofφ_(i)=2π*D/λi*cos(LOB_(i))

A typical intermodulation product would be the 3^(rd) order productcreated by two large signals. Its “true frequency” would be at 2*F1+F2and the resulting intermodulation product would have a phase differencebetween elements on the antenna array of 2*φ₁+φ₂. However if the “truefrequency” is above the Nyquist frequency of the system (i.e. >½ thesampling rate) it will be aliased to some apparent frequency less thanNyquist. Similarly, the measured phase angle in a real system can onlybe between ±π. These two phenomena have the overall results ofrandomizing the frequency and phase of all intermodulation products overthe range 0 to F_(max) and from ±π respectively.

However real signals come from real directions and at any spot frequencythe maximum phase shift that can be measured between array elements isφ_(max)=2π*(D/λ)

For a wide band array the spacing is set so D=½λ_(max) in order to avoidambiguities and the range of “real φ” can be seen to be proportional tofrequency.

Referring to FIG. 6 only 50% of the “phase-frequency” range has physicalmeaning, and as no real signal can have a phase angle between elementswhich are outside of this region, then any “signal” with such a phaseangle must be spurious and can be ignored.

It is anticipated that the intermodulation products are evenlydistributed within the phase-frequency space, and hence it is thereforeanticipated that 50% of all intermodulation products can be removedusing a simple, linear (one-dimensional) array of antennae.

Extending this reasoning into two dimensions, a two-dimensional arraywill allow a simple filter to remove 1-π/12, or about 74% of allintermodulation products generated by the ADCs. A three-dimensionalarray would permit 1-π/24 or about 87% of all intermodulation productsto be removed since they do not come from physically realizablespace—i.e. they are “ghosts”.

Although three-dimensional arrays are physically realizable in themicrowave bands, this embodiment using digital array architecture is inthe H.F. band. In this band the 87% “de-ghosting” level is seen as anupper limit that may be achievable with advanced antenna arrayarchitectures whilst the 74% de-ghosting is a lower level that can beachieved readily with a simple two-dimensional, or crossed array.

Use of High Order Statistics

It has been described that it is possible using a spatial array of ADCsto remove the majority of intermodulation products and to separate mostSOIs from the remaining intermodulation products since they will seem tocome from different directions.

However, there is still a chance that a real signal will coincide withan intermodulation product in the full Frazel space (i.e. samefrequency, azimuth and elevation). If this occurs it will then benecessary to use a High Order Statistical (HOS) based separation whichcan exploit the fact that the intermodulation signals will bestatistically quite different from almost all real signals. A number ofdifferent HOS techniques are available —usually based on the use of 4thorder cumulants. JADE is arguably the best known.

The statistical difference is mainly brought about by the process bywhich an intermodulation product is formed. For example, one of thelarge intermodulation products is the third harmonic of a signal (i.e.3F), and if the original SOI were a BFSK signal with two tones separatedby 1 kHz the resulting third harmonic would have 3 kHz separations andhence different statistics.

Noise in ADC Systems

Even if most of the intermodulation products can be removed, and thenco-channel algorithms used to separate those remaining from SOIs, thereis still a finite amount of noise generated in an ADC and this noisefloor may determine the ultimate dynamic range available for the array.In determining the noise floor of the ADC's the main considerations willbe:

-   -   1. For a typical ADC the noise floor is about 2 bits below the        highest spurs    -   2. For an array with N elements, a reasonable assumption is that        the SNR will increase by √N since signals add coherently and        noise incoherently.

3. In an array in which the total noise is distributed over all Frazelbins, the total noise on any one receiver channel could be quite low.

4. The actual noise may be coloured and may seem to favour some specificdirections, which may reduce the apparent noise in other directions. Itshould be noted that the actual, physical noise may be directional (e.g.lightning strikes or power line noise in the RF environment, or highlycorrelated noise due to jitter on the sampling clock) and may not appearevenly distributed throughout Frazel space.

5. The System Noise Floor may be dominated by rounding errors in thesignal processing which is determined principally by the arithmeticresolution and the number of operations required in the algorithm.

Given these factors it becomes difficult to determine the actual noisefloor and hence the maximum available dynamic range until the systemdesign is finalized. However, it would be preferable to produce areceiving system with −20 dbm signals at the input, and to still be ableto detect and demodulate conventional narrow band signals such as Morsecode at −150 dbm. This would require a 130 dB dynamic range, a figurethat may be at least 30 dB higher than can be achieved with currenttechnology, but would appear achievable.

One of the interesting features of the digital approach to a receiverarray is that many of the traditional metrics for measuring the RFperformance are not readily applicable. For example the most widely usedmetric in conventional receivers is the Spurious Free Dynamic Range, butas described many of the birdies are ‘ghosts’ and:

-   -   1. if spatially separate, can be removed using spatial        processing to separate them from the signals of interest; and    -   2. if co-existing in the same Frazel cell with an SOI, they can        be identified and removed using HOS algorithms.

Given this, the best metric is not the SFDR of the system, but ratherthe probability of detecting and being able to demodulate a signal at agiven power level in a specific Frazel cell. Thus the operating dynamicrange can be much greater than the SFDR of the system and for thepurposes of this specification, it is assumed that the “effective SFDR”of the receiver is a sensible metric for comparison purposes betweendigital and non-digital systems.

Performance of an Array

Having looked at the main parameters that are being considered, the bestADCs are achieving aperture jitters which approach 0.5 picoseconds aswas shown in the study Walden “ADC Survey and Analysis” IEEE SAC vol 14,#4 at FIG. 5. The best ADC currently available with a 75 MHZ-samplingrate offers an SFDR of almost 14 bits (i.e. 84 dB).

When using the invention co-channel separation algorithms havedemonstrated that a simple 8-channel system can realize major benefits.A typical example would be a weak signal brought from more than 20 dBbelow a large signal on the same frequency to greater than 20 dB abovethe signal. This suggests that an “array gain” of greater than 40 dB wasbeing achieved. When a 32-channel system is used it could be expectedthat the performance improvement could be equivalent to an additional 8bits and implies an effective SFDR of 20 bits or 120 dB. This isapproaching the required 130 dB dynamic range.

A concern with the direct digitising array concept is that theprocessing load is very high. As was shown in an earlier part of thespecification, the processing load is in the Tera-flops/Tera-ops region(Tflops/Tops). Although this is high it should be noted that:

-   -   1. Processing power appears to double every 18 months or so, and        processing that is impractical today may be possible in the near        future.    -   2. Much of the processing is regular and can be done in parallel        and therefore can be implemented in dedicated signal processing        chips    -   3. It is possible to produce a systolic array capable of        operating at 10 Gops in 10 square mm of silicon using 0.35        micron Complementary Metal Oxide Semiconductor (CMOS) technology        today and as such 1 tops of processing would require a bout 10        chips using 0.25 micron technology, which could be implemented        on a standard VERSA Module Eurocard (VME) card.

For well-defined operations such as frequency filtering andchannelisation, it will be relatively easy to implement the requiredcomputing rates. However, for algorithms that are more sophisticatedsuch as JADE, or a HOS algorithm, they can be implemented using acluster of general purpose computers, but the high rate of data I/O maybe significant.

Although there are a number of major issues that need to be resolved, itis believed that:

-   -   1. a direct digitising array system will perform better than an        individual channel,    -   2. the performance will improve as the array size increases, and    -   3. the actual performance of the system will depend on the        number of channels, the fidelity of the ADCs and the subsequent        processing.

It is anticipated that a direct digitising array processor willoutperform existing analogue based receiving systems for the H.F. band,and offer new possibilities in higher frequency domains.

It will be appreciated by those skilled in the art, that the inventionis not restricted in its use to the particular application described andneither is the present invention restricted in its preferred embodimentwith regard to the particular elements and/or features described ordepicted herein. It will be appreciated that various modifications canbe made without departing from the principles of the invention,therefore, the invention should be understood to include all suchmodifications within its scope.

1. An analogue to digital converter apparatus for converting one or moreanalogue signals arriving at a plurality of spatially separated receiverelements, the apparatus comprising: a respective plurality of receiveelements and analogue to digital converters (ADC's), each receiveelement and ADC exhibiting non-linear effects in the analogue and/ordigital processes of receiving and converting received analogue signalsfrom respective receive elements and generating respective ADC outputsthat are digital representations of received signals plus spurioussignals resulting from said non-linear effects: processing meansconfigured to identify in said ADC outputs said spurious signals by (a)analysis of the phase relationships of said ADC outputs according to thespatial and phase relationships between said receive elements; and/or(b) analysis by High Order Statistical techniques of said ADC outputs;and a filter to remove identified spurious signals.
 2. An analogue todigital conversion apparatus according to claim 1, wherein the processis configured such that said analysis of said phase relationships andsaid High Order Statistical analysis are performed in parallel to, or inseries with each other.
 3. An analogue to digital conversion apparatusfor converting to a digital representation one or more analogue signalsarriving at a receive element providing a receive output, the apparatuscomprising: one or more variable phase delay means for generating aplurality of phase delayed versions of said receive output, one or morerespective analogue to digital converters (ADCs) for the or eachvariable phase delay means, wherein said receive element, variable phasedelay means and each ADC exhibits non-linear effects in the analogueand/or digital processes of receiving, delaying and/or convertinganalogue signals and generating respective ADC outputs which are thedigital representations of receive signals and spurious signalsresulting from said non-linear effects; processing means configured toidentify said spurious signals by (a) analysis of the phaserelationships of said ADC outputs according to the phase delaysintroduced by said variable phase delay means, and/or (b) High OrderStatistical analysis of said ADC outputs and; filter means to removeidentified spurious signals.
 4. An analogue to digital conversionapparatus according to claim 3, wherein said analysis of said phaserelationships and said High Order Statistical analysis are performed inparallel to, or in series with each other.
 5. An analogue to digitalconversion apparatus according to claim 4, further comprisingchannelisation means to divide the said ADC outputs into multiplechannels prior to processing and filtering.
 6. An analogue to digitalconversion apparatus according to claim 5, further comprising asynthesis means to reconstitute two or more of said multiple channelsinto a processed and filtered digital representation of said one or moreanalogue signals.
 7. A method for identifying and filtering spurioussignals from the digital representations of one or more signals,comprising: (a) receiving at a plurality of spatially separated receiverelements, one or more analogue signals, each said receiver elementcontributing spurious signals as a result of the non-linear propertiesof the analogue process of receiving said one or more signals; (b)receiving at a respective plurality of analogue to digital converters(ADC's) the output of a said receiver element, each ADC contributingspurious signals as a result of the non-linear properties of theanalogue and digital processes conducted by said ADC for converting theoutput of a respective receive element into digital representationswhich include said signals and spurious signals; (c) processing saiddigital representations to identify therein said spurious signals by (i)analysis of the phase relationships of said ADC outputs according tosignals and spurious signals to the spatial and phase relationshipsbetween said receive elements; and/or (ii) performing High OrderStatistical analysis of said ADC outputs; and (d) filtering to removeidentified spurious signals.
 8. A method according to claim 7, whereinsaid analysis of said phase relationships and said High OrderStatistical analysis are performed in parallel to, or in series witheach other.
 9. A method for identifying and filtering spurious signalsfrom the digital representations of one or more signals, comprising: (a)receiving at a receiver element one or more analogue signals providing areceive output, said receiver element contributing spurious signals as aresult of the non-linear properties of the analogue process of receivingsaid one or more signals; (b) receiving at one or more variable phasedelay means said receiver output and generating a plurality of phasedelayed versions of said output, said variable phase delay meanscontributing spurious signals as a result of the non-linear propertiesof the analogue process of generating said phase delayed versions; (c)providing an analogue to digital converter (ADC) for the or eachvariable phase delay means, each ADC contributing spurious signals as aresult of the non-linear properties of the analogue and digitalprocesses conducted by said ADC for converting the output of arespective phase delay means into digital representation; (d) processingsaid digital representations to identify said spurious signals by (i)analyzing the phase relationships of said ADC outputs according to thephase delays introduced by said variable phase delay means, and/or (ii)performing High Order Statistical analysis of said ADC outputs; and (e)filtering to remove said identified spurious signals.
 10. A methodaccording to claim 9, wherein said analysis of said phase relationshipsand said High Order Statistical analysis are performed in parallel to,or in series with each other.
 11. A method according to claim 7, 8, 9 or10, wherein creating said digital representations of step (c) includesdividing said digital representations into multiple channels.
 12. Amethod according to claim 11, comprising the further step: (f)synthesizing said digital representations provided by said filteringstep (e) to reconstitute two or more of said multiple channels into aprocessed and filtered digital representation of said one or moreanalogue signals.